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212

XMEGA A [MANUAL]

8077I–AVR–11/2012

Figure 19-13.TWI slave operation.

The number of interrupts generated is kept to a minimum by automatic handling of most conditions. Quick command can

be enabled to auto-trigger operations and reduce software complexity.

Promiscuous mode can be enabled to allow the slave to respond to all received addresses.

19.6.1 Receiving Address Packets

When the TWI slave is properly configured, it will wait for a START condition to be detected. When this happens, the

successive address byte will be received and checked by the address match logic, and the slave will ACK a correct

address and store the address in the DATA register. If the received address is not a match, the slave will not

acknowledge and store address, and will wait for a new START condition.

The slave address/stop interrupt flag is set when a START condition succeeded by a valid address byte is detected. A

general call address will also set the interrupt flag.

A START condition immediately followed by a STOP condition is an illegal operation, and the bus error flag is set.

The R/W direction flag reflects the direction bit received with the address. This can be read by software to determine the

type of operation currently in progress.

Depending on the R/W direction bit and bus condition, one of four distinct cases (S1 to S4) arises following the address

packet. The different cases must be handled in software.

19.6.1.1 Case S1: Address packet accepted - Direction bit set

If the R/W direction flag is set, this indicates a master read operation. The SCL line is forced low by the slave, stretching

the bus clock. If ACK is sent by the slave, the slave hardware will set the data interrupt flag indicating data is needed for

transmit. Data, repeated START, or STOP can be received after this. If NACK is sent by the slave, the slave will wait for

a new START condition and address match.

19.6.1.2 Case S2: Address packet accepted - Direction bit cleared

If the R/W direction flag is cleared, this indicates a master write operation. The SCL line is forced low, stretching the bus

clock. If ACK is sent by the slave, the slave will wait for data to be received. Data, repeated START, or STOP can be

received after this. If NACK is sent, the slave will wait for a new START condition and address match.

19.6.1.3 Case S3: Collision

If the slave is not able to send a high level or NACK, the collision flag is set, and it will disable the data and acknowledge

output from the slave logic. The clock hold is released. A START or repeated START condition will be accepted.

ADDRESS

DATA

A/A

DATA

SLAVE ADDRESS INTERRUPT

SLAVE DATA INTERRUPT

Collision

(SMBus)

A/A

Release

Hold

Interrupt on STOP

Condition Enabled

Driver software

The master provides data

on the bus

Slave provides data on

the bus

Diagram connections

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